1. Field of the Invention
This invention relates generally to semiconductor input/output circuits, and more particularly to feed-forward circuits for reducing delay through input buffers in integrated circuits (ICs).
2. Description of the Related Art
In today's world of ICs with ever smaller devices, board voltages have not been reduced at the same rate as IC voltages. As a result, there is a need for tolerant input/output (I/O) designs that can tolerate higher board voltages than the IC's internal voltage. That is, the input section of an I/O circuit generally requires some form of protection. For example, FIG. 1 shows an exemplary printed circuit board (PCB) configuration 100. The PCB configuration 100 includes a PCB 102 and a plurality of chips 104a–104b disposed on the PCB 102. Each chip 104a–104b includes an I/O ring 106a–106b that provides I/O operations for the chip 104a–104b. Although only two chips 104a–104b are illustrated in FIG. 1, it should be borne in mind that a typical PCB configuration 100 will include many chips disposed throughout the PCB 102.
The various chips on the PCB 102 may operate at different voltages. In this example, chip 104a is a 0.13 micron chip that operates at 1.2 volts, and chip 104b is a 0.25 micron chip that operations at 2.25 volts. A voltage mismatch occurs when chip 104b drives a signal at 2.25 volts, but chip 104a only has a 1.2 volt internal supply. Thus, the I/O devices within the I/O rings 106a–106b must be designed to handle such a voltage mismatch.
The I/O rings 106a–106b generally have voltages greater than the internal supply voltages of the chips. In this example, the ring voltage of I/O ring 106a is 3.3 volts and the ring voltage of I/O ring 106b is 5 volts. Thus, in the above example, the I/O ring 106b of chip 104b provides a 5 volt signal to the I/O ring 106a of chip 104a, which operates at 3.3 volts. After converting the 5 volt signal to the ring operating voltage of 3.3 volts, the I/O ring 106a converts the 3.3 volt signal to the core voltage of chip 104a, which is 1.2 volts.
FIG. 2 is a schematic diagram showing a prior art I/O ring circuit 200. The prior art I/O circuit 200 includes a pad I/O 204 providing a signal to a plurality of input buffers 202a–202b operating at ring voltage. An input buffer inverter 206 is used to convert the ring voltage at node 210 to a core voltage at node 212. A further input buffer 208, which operates at the core voltage, is included to provide drive current for driving heavily loaded core nodes.
As inverter 206 is driven by inverter 202b, which operates at ring voltages, inverter 206 must be constructed of ring transistors. Unfortunately, the ring transistors have high threshold voltages due to the higher operating voltage requirements. The high threshold voltages, high input voltage, and low supply voltage for inverter 206 cause the high going transition on node 212 to be slow. This is due to the reduced core voltage (VDD−VTP), and the delayed turn-on time for the ring p-channel transistor in inverter 206. FIG. 3 is a schematic diagram showing a prior art inverter 206 that converts from a ring voltage to a core voltage. As illustrated in FIG. 3, the inverter 206 includes a p-channel ring transistor 300 having a first terminal coupled to a core VDD, a gate coupled to node 210, and a second terminal coupled to node 212 and an n-channel transistor 302. The n-channel transistor 302 includes a first terminal coupled to the p-channel transistor 300, a gate coupled to node 210, and a second terminal coupled to ground.
In operation, node 210 is the Ring VDD when node 210 is driven HIGH, which is higher than the Core VDD. Thus, when node 210 is HIGH, Ring VDD is present at the gate of the p-channel ring transistor 300 and Core VDD is present at the source of the p-channel ring transistor 300. Using voltages from the example of FIG. 1, Ring VDD can be 3.3volts and the Core VDD can be 1.2 volts. In addition, the p-channel ring transistor 300 can be a 3.3 voltage transistor with a 700 mV threshold (referred to herein as VTP). In this example, node 210 must fall to a voltage of Core VDD−VT before the p-channel ring transistor 300 turns ON. Thus, in the above example, node 210 must fall to 1.2 V−0.700V=0.5 V before the p-channel ring transistor 300 turns ON. That is, node 210 must fall from 3.3 V to 0.5 V before the p-channel ring transistor 300 starts to turn ON. As a result, the p-channel ring transistor 300 is slow in driving node 212 HIGH.
In view of the foregoing, there is a need for a feed-forward circuit for reducing the delay through an input buffer. The feed-forward circuit should allow fast switching from ring voltage to core voltage when the ring voltage is much higher than the core voltage.